AX CPU Number of issues

Product Discussions ADC - Application Delivery
1

Posted by fitwate

============= Version Info ================= AX Series Advanced Traffic Manager AX2100 Copyright 2007-2010 by A10 Networks, Inc. All A10 Networks products are protected by one or more of the following US patents and patents pending: 7716378, 7675854, 7647635, 7552126, 20090049537, 20080229418, 20080040789, 20070283429, 20070271598, 20070180101

Advanced Core OS (ACOS) version 2.4.3-P1-SP1, build 3 (Aug-02-2010,17:00) Booted from compact flash primary image Serial Number: AX2114110xxxxx aFleX version: 2.0.0 Hard disk primary image (default) version 2.4.3-P1-SP1, build 3 Hard disk secondary image version 2.2.4-p6, build 1 Compact flash primary image (default) version 2.4.3-P1-SP1, build 3 Compact flash secondary image version 2.2.4-p6, build 1 Last configuration saved at Dec-30-2010, 01:17 Hardware: 8 CPUs(Stepping 10), Dual 146G Hard disks Memory 4155 Mbyte, Free Memory 2739 Mbyte Current time is Dec-30-2010, 01:47 The system has been up 0 day, 0 hour, 28 minutes

============= CPU Usage Info (show cpu) =============== Time: 01:47:13 GMT Thu Dec 30 2010 1Sec 5Sec 10Sec 30Sec 60Sec -------------------------------------------------------- Control 41% 7% 8% 9% 8% Data1 0% 0% 0% 0% 0% Data2 0% 0% 0% 0% 0% Data3 0% 0% 0% 0% 0% Data4 0% 0% 0% 0% 0% Data5 0% 0% 0% 0% 0%

A total of eight cpu(show version), But the show cpu found only six, the other is the role of 2 cpu? Where can I find? Which version of this phenomenon will be?

2

Posted by pnicholson

For non-FPGA models, such as the AX 2100, you may see less data CPUs than you expected, as one or more will be dedicated to the High Performance Driver software to provide the FPGA functions.

This is by design to meet the performance metrics for the particular model in question, however all are used. You would not see this on the FPGA models.

Paul.

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Posted by fitwate

Thank you for your explanation Can you explain FPGA in detail? Can you explain ASICs in detail?

Difference between FPGA and ASICs?

Thank you very much!

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Posted by pnicholson Hi, We actually have some good published information available already The two papers which include FPGA/ASIC information are: www.a10networks.com/resources/files/WP-ACOS.pdf www.a10networks.com/resources/files/SB-ACOS.pdf I would also read this paper as it builds on the previous papers and covers the 64-bit advantage (though not directly applicable to the FPGA/ASIC part of your question): www.a10networks.com/forms/register.SB-64-bit.php If you want more detail we can arrange for your local SE to discuss it with you as well. Thanks, Paul.

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Posted by fitwate

I will carefully read the information above,Thank you very much.

FPGA is a flexible distribution of the traffic to the cpu，FPGAs offer near-ASIC speeds with the ability to be reprogrammed with new logic as the application needs evolve。

ASIC is a hardware, such as Switching/Routing、ssl 、compression